The inventive concept relates to jitter of a clock signal, and more particularly, to a circuit and method of measuring clock jitter.
Digital circuits may operate in synchronization with a clock signal. For example, the digital circuits may each include a plurality of flip-flops, and each of the plurality of flip-flops may operate in response to an edge of the clock signal. Also, function blocks which operate in synchronization with the clock signal may have different operating frequencies, and thus, a plurality of clock signals having various frequencies may be generated.
A clock signal is intended to be periodical, but due to various factors, in general the clock signal will deviate from true periodicity, and this deviation is referred to as “jitter”, or more specifically in the case of a clock signal as “clock jitter.” Due to a design which is made by a designer in consideration of an amount of jitter in a clock signal, the performance of a function block is limited by the jitter of the clock signal. The amount of jitter in the clock signal may vary among dies, or within a die, due to variations of a semiconductor manufacturing process, and may vary with a temperature of a digital circuit or a voltage applied to the digital circuit. The amount of jitter may be determined based on the performance of a circuit (for example, a phase locked loop (PLL)) which generates the clock signal.